1. Field of the Invention
The present invention relates to the field of memory devices in integrated circuits, and more particularly, the present invention relates to circuits and method for testing memory cells in such memory devices. More specifically, the present invention relates to a method and circuit for stress testing a memory cell of a static random access memory (SRAM) device.
2. Description of Related Art
A typical static random access memory (SRAM) circuit has arrays of memory cells that include word lines, a read/write circuit coupled to each array, and an access control circuit. The read/write circuit provides the capability of writing data or bit values to each memory cell. The access control circuit drives a plurality of word lines to perform read and write operations. Each memory cell has a pair of cross-coupled inverters that are utilized to store a digital value (e.g., a high value or a low value). For a memory cell of the SRAM circuit, a circuit path along one of the cross-coupled inverters holds the digital value and typically includes a first p-type transistor, a first n-type transistor, and a first pass-gate transistor. Another circuit path along another one of the cross-coupled inverters usually holds the complementary digital value and has a second p-type transistor, a second n-type transistor, and a second pass-gate transistor. The pass gate transistors are used to couple the two cross-coupled inverters to a bit line and a complementary bit line of the SRAM cell. Therefore, one SRAM circuit path generally maintains the digital value while another SRAM circuit path generally maintains the complementary digital value.
The SRAM circuit is generally made as an integrated circuit (IC) according to an integrated circuit process. The IC process involves the formation of semiconductor and metal structures for the SRAM circuit. Diffusion regions and polysilicon structures within the semiconductor structures typically form the transistors of the SRAM circuit. Metal structures are utilized to provide electrical connections between the transistors and other components of the SRAM circuit. The typical IC process involves the formation of numerous electrical contacts for each memory cell, and the contacts may be formed where diffusion regions, polysilicon structures, metal interconnecting structures, and/or vias of the transistors meet.
However, the typical IC involves defects occurring in the semiconductor and metal structures during the IC manufacturing and fabrication process. For example, the defects in IC fabrication process may exist and cause xe2x80x9cweakxe2x80x9d contacts or failures in the memory cells or in the individual transistors of the memory cells. Two types of defects generally exist for a memory cell: a symmetric defect or an asymmetric defect. A symmetric defect impairs the performance of the pair of cross-coupled inverters of a memory cell while an asymmetric defect impairs only one of the cross-coupled inverters. For example, a defective contact in a power supply line, which supplies power to the entire memory cell, is considered a symmetric defect since the pair of cross-coupled inverters is denied power. A defect in a p-transistor within one of the cross-coupled inverters is an example of an asymmetric defect since the defect only affects one of the cross-coupled inverters.
Various testing procedures exist to test the quality of the IC and to detect defects in the IC with the SRAM circuit. One such test is to place the IC having the SRAM circuit into a specialized IC tester. The IC tester writes data into the SRAM circuit and immediately reads the data therefrom to verify the data stored therein. If the data read from the SRAM circuit does not match the data written to the SRAM circuit, then the SRAM circuit is deemed defective. This type of test procedure, however, does not detect manufacturing defects of the memory cell that cause data retention problems that occur over a relatively long period of time. For example, a memory cell for the SRAM device having a defective p-transistor within one of the cross-coupled inverters may be able to retain a high voltage value for only a short time period. The high voltage maintained at the nodes of the memory cell would discharge through diffusion regions of the transistors of the memory cell. A defective p-transistor would then be able to maintain the high voltage for a short time period but would not be able to maintain the high voltage level for a long period of time.
One known way of detecting such data retention defects is to provide the IC tester with a delay that is long enough to allow such a defective memory cell to discharge. However, the time between when the IC tester writes the data and reads the data is increased so that the data retention defects are detectable. Such delays significantly increase the testing time of each IC. Multiple IC testers would then have to be used in parallel to decrease the overall testing time of all the ICs, but the use of multiple IC testers, which are relatively expensive, increase the overall costs of manufacturing and testing the ICs with SRAM devices.
Another prior art method of testing ICs having SRAM circuits involves coupling a xe2x80x9cweak writexe2x80x9d test circuit to each array of memory cells. The xe2x80x9cweak writexe2x80x9d test generally involves using a separate test circuit for applying a pre-determined voltage amount to the memory cell to test the existence of excess resistance or leakage within the transistors and transistor paths of the memory cell. The pre-determined voltage amount is set at a value in which the applied voltage will not affect the value of a good memory cell but will change the value of a defective memory cell. U.S. Pat. No. 5,559,745 to Banik et al. (xe2x80x9cBanikxe2x80x9d) assigned to Intel Corporation, Santa Clara, Calif., discloses such an exemplary xe2x80x9cweak writexe2x80x9d circuit and method.
Prior art FIG. 1 shows a memory cell 16 being tested by a xe2x80x9cweak writexe2x80x9d test circuit 18 according to Banik. Memory cell 16 is a typical SRAM cell that includes a plurality of transistors T1 to T6 configured in a manner to form cross-coupled inverters as shown in prior art FIG. 1. Fabrication defects in the transistor(s) or along the transistor path(s) may reduce the strength of pull-up p-type transistors T1 and T2 and/or the pull-down n-type transistors T3 and T4, and these defects are a potential source of data retention defects. Other types of fabrication defects are from leakage paths at node N1 and/or node N2, which may also be potential sources of data retention defects. Bit line pair 8 consists of a bit line 10 and a complementary bit line, bit bar line 12, as shown in prior art FIG. 1. Transistor T5 is a pass gate transistor, which couples a node NI to bit line 10. Transistor T5 is also coupled to word line (xe2x80x9cWLxe2x80x9d) 14. Similarly, the transistor T6 is another pass gate transistor that connects a node N2 to bit bar line 12. Transistor T6 is also coupled to word line (xe2x80x9cWLxe2x80x9d) 14. Transistors T5 and T6 and, in turn, memory cell 16 are activated by word line 14.
Various contacts, such as contacts CA to CJ, exist in circuit paths of memory cell 16. Defects may exist or be generated from contacts, such as contacts CA to CJ, in memory cell 16. Defective contacts may result in the necessary or proper connection not being provided between the integrated circuit structures or may provide a highly resistive connection compared to other contacts. The lack of proper connections and/or the existence of highly resistive connections may cause long-term data retention problems for memory cell 16.
xe2x80x9cWeak writexe2x80x9d test circuit 18 requires the passing of two separate tests in order to verify whether memory cell 16 is not defective. The first test is the weak writing of a zero (xe2x80x9c0xe2x80x9d) digital value into memory cell 16. A one (xe2x80x9c1xe2x80x9d) digital value is first written into memory cell 16. xe2x80x9cWeak writexe2x80x9d test circuit 18 is then activated to attempt to weak write a zero (xe2x80x9c0xe2x80x9d) digital value into memory cell 16. The digital value of memory cell 16 is thereafter read to determine whether or not the one (xe2x80x9c1xe2x80x9d) digital value has flipped to the zero (xe2x80x9c0xe2x80x9d) value. The second test is the weak writing of a one (xe2x80x9c1xe2x80x9d) into memory cell 16. A zero (xe2x80x9c0xe2x80x9d) digital value is first written into memory cell 16. xe2x80x9cWeak writexe2x80x9d test circuit 18 is activated to attempt to weak write a one (xe2x80x9c1xe2x80x9d) digital value into memory cell 16. The digital value of memory cell 16 is thereafter read to determine whether or not the zero (xe2x80x9c0xe2x80x9d) digital value has flipped to the one (xe2x80x9c1xe2x80x9d) digital value.
If the digital value of memory cell 16 and bit line 10 for memory cell 16 are of high values, then a first set of components in xe2x80x9cweak writexe2x80x9d test circuit 18 includes transistors for performing the xe2x80x9cweak writexe2x80x9d zero test. The first set of components includes at least a discharging transistor T8 coupled to bit line 10 and a charging transistor T11 coupled to complementary bit line 12. A first test control line 20 is required to provide the signal for activating the first set of components. However, if the digital value of memory cell 16 and bit line 10 for memory cell 16 are of low values, then the second set of components in xe2x80x9cweak writexe2x80x9d test circuit 18 includes transistors for performing the xe2x80x9cweak writexe2x80x9d one test. This second set of components includes at least a charging transistor T10 coupled to bit line 10 and a discharging transistor T9 coupled to complementary bit line 12. A second test control line 22 is also required to provide the signal for activating the second set of components. As shown in prior art FIG. 1, two generally different sets of components (e.g., transistor set that includes transistors T8 and T11 and transistor set that includes transistors T9 and T10) and two respective test control lines 20 and 22 are required to perform the two separate tests. Each of the two different sets of components includes at least a transistor for charging a bit line and another transistor for discharging the other respective bit line.
One disadvantage of xe2x80x9cweak writexe2x80x9d circuit 18 and the xe2x80x9cweak writexe2x80x9d method is that they require driving currents to be carefully matched to memory cell 16. If the currents are not carefully matched and xe2x80x9cweak writexe2x80x9d circuit 18 and method overdrive memory cell 16 when xe2x80x9cweak writingxe2x80x9d it, then memory cell 16 may be erroneously detected as defective and unnecessarily thrown out. On the other hand, if xe2x80x9cweak writexe2x80x9d circuit 18 and method underdrive memory cell 16 when xe2x80x9cweak writingxe2x80x9d it, then memory cell 16 may be erroneously passed as a good cell when, in fact, it is a defective cell.
Another disadvantage of xe2x80x9cweak writexe2x80x9d circuit 18 and method is that they require the use of two sets of components and two respective test control lines to perform both the xe2x80x9cweak writexe2x80x9d zero test and the xe2x80x9cweak writexe2x80x9d one test. The use of two sets of components and two test control lines add to the overall space and cost of the memory device. Also, utilization of additional components, transistors, and test control lines add to the complexity of the circuit design and increase the possibilities of circuit errors and problems. The use and management of two sets of components also become complicated. The two tests (e.g., xe2x80x9cweak writexe2x80x9d zero test and the xe2x80x9cweak writexe2x80x9d one test) both need to be done, but individual and separate execution is required for each of the two tests. xe2x80x9cWeak writexe2x80x9d circuit 18 and method have the shortcoming of not being able to automatically identify or self determine which test (e.g., xe2x80x9cweak writexe2x80x9d zero test or xe2x80x9cweak writexe2x80x9d one test) is to be performed and executed.
A further prior art method for testing ICs with SRAM circuits is to couple a transistor to each and every bit line of a memory cell. The transistor is activated to pull-down the voltage level on a high bit line. However, this method also requires the use of many additional transistors (e.g., one transistor for each bit line). Each transistor also requires driving currents to be carefully matched to the memory cell or device. If the currents are not carefully matched and the transistor overdrives the memory cell during the test, then the memory cell may be erroneously detected as defective and unnecessarily thrown out. On the other hand, if the transistor underdrives the memory cell during the test, then the memory cell may be erroneously passed as a good cell when, in fact, it is a defective cell. The additional transistors substantially add to the space and cost of the memory device. Also, the manner for controlling and activating the transistors becomes necessary and complex in that logic or methodology must be implemented to determine which transistors are to be activated at which times and/or under which conditions. The transistors are also not configured in a manner to automatically identify or self determine when to activate to perform the appropriate test.
The present invention recognizes the desire and need for a memory test circuit, which does not have to carefully match driving currents to the memory cell or device. The present invention also recognizes the desire or need for a memory test circuit which is simple in design and requires a minimal number of components. The use of less components minimizes the overall space and cost of the memory device and reduces the complexity of the circuit design, which lowers the possibilities of circuit errors and problems. The present invention further recognizes the need or desire for the memory test circuit automatically identifying or self-determining which test (e.g., write test zero or write test one) is to be executed and performed. Automatic identification or self determination of the appropriate test would eliminate or minimize the logic, methodology, or programmed/manual control for having to determine which test is to be executed. The present invention overcomes the problems and disadvantages in accordance with the prior art.
A stress test circuit and method for static random access memory (xe2x80x9cSRAMxe2x80x9d) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.
An object and advantage of the present invention is to provide a stress test circuit for memory cells (e.g., SRAM cells) of a memory device (e.g., a SRAM device) in which the stress test circuit includes a stress test component having a resistance element and a switch component to electrically couple the resistance element between a bit line and a complementary bit line both driven by a word line of an SRAM cell storing a digital value written therein and the stress test circuit creates an electrical path causing a defective memory cell to change in value.
An aspect and advantage of the present invention is to provide a stress test component that is a transistor coupled to the bit line, the complementary bit line, and a stress control voltage for controlling activation of the stress test component.
Another aspect and advantage of the present invention is that the memory cell may be a multi-port cell and the memory cell includes two cross-coupled inverters wherein a first one of the two cross-coupled inverters has a first p-type transistor/a first resistor and a first n-type transistor and a second one of the two cross-coupled inverters has a second p-type transistor/a second resistor and a second n-type transistor; a pass-gate transistor that couples a node between the first p-type transistor/first resistor and the first n-type transistor to the bit line; and another pass-gate transistor that couples another node between the second p-type transistor/second resistor and the second n-type transistor to the complementary bit line.
A further aspect and advantage of the present invention is that when the digital value is a high value and the complementary digital value is a low value, a voltage on a SRAM circuit path defined by the first p-type transistor/first resistor, the first n-type transistor, and the pass-gate transistor is pulled down by a stress current and another voltage on another SRAM circuit path defined by the second p-type transistor/second resistor, the second n-type transistor, and the another pass-gate transistor is pulled up by the stress current to test whether a defect in the SRAM cell exists to change the digital value of the SRAM cell to the opposite value.
A still further aspect and advantage of the present invention is that when the digital value is a low value and the complementary digital value is a high value, a voltage on a SRAM circuit path defined by the first p-type transistor/first resistor, the first n-type transistor, and the pass-gate transistor is pulled up by a stress current and another voltage on another SRAM circuit path defined by the second p-type transistor/second resistor, the second n-type transistor, and the another pass-gate transistor is pulled down by the stress current to test whether a defect in the SRAM cell exists to change the digital value of the SRAM cell to the opposite value.
Still another aspect and advantage of the present invention is that the stress control voltage applied to activate the stress test component is varied to change stress amounts applied to the memory device.
A still further aspect and advantage of the present invention is to also provide the stress test circuit with a balanced excessive resistance detector coupled to the bit line and the complementary bit line for detecting and indicating the memory cell as being defective when a generally equal amount of excessive resistance exist along the bit line and the complementary bit line.
Another object and advantage of the present invention is to provide a method of testing a memory cell (e.g., SRAM cell) of a memory device (e.g., SRAM device) which includes the steps of writing a digital value in the memory cell of the memory device in which the memory cell is driven by a bit line and a complementary bit line accessed through a word line and has an SRAM circuit path for maintaining and storing the digital value and another SRAM circuit path for maintaining and storing a complementary digital value; stressing the memory cell by electrically coupling a resistance element between the bit line and the complementary bit line; and reading the digital value in the memory cell accessed through the word line to determine whether the digital value has changed to an opposite value.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.